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Copyright January 28th 1996 - Updated October 29th 2015   ..........    Brought to you by Unitech Electronics Pty. Ltd.

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Manufacturers       Basic Pin outs       Block-layout       Timing graphs

Internals Circuit       Pin functions       NE-555 pocket-tester       NE-555 time-constants

NE-555 discharge-path       NE-555 monostable       NE_555_astable-or-mulitvibrator       NE-xxx-data-downloads

Following in the footsteps of the "primitive" but quite successful 4 pin OM802 timer IC manufactured by the original SIGNETICS ITT - GEMINI chip fabrication plants way back in 1969 / 1970, a new and very innovative I.C. known as the " NE-555 " timer I.C. was released to the market, being introduced around May 1971 by the then Signetics Corporation, later to be taken over by Philips Semiconductor, then more recently, NXP SEMICONDUCTOR, as a division of Philips.   It then became commonly known as "triple-five", the NE-555 / SE-555 which we all know today as the "The Ubiquitous Timer chip" and it was also the very first mass-produced commercially produced timer IC available at that time. The design team could not have realised how sought after this chip was and I am sure many of you reading this will agree, it is without a doubt, the most useful " chip concept " that has endured the past almost two decades of consistent sales and what product shelf life it has had !        No one could have realised back in 1970,  just how brilliantly successful it would be,  lasting well over 25 years and manufactured by so many  companies even today in   May 1996  and it is very much in demand by the " electronics Industry " today in August 2011, some 40 years later.

CLICK THE OM802 Timer chip OM 802 CHIP

The NE-555 would prove to be a  " hit   "  and provide Electronic Engineers, Circuit Designers and a host of    "Hobby Tinkerers"  with a relatively novel and highly economical timer chip using just a bare minimum of external components thus resulting in very stable at timing, all the way up to its maximum timing and maximum oscillating frequency of ( at the time ) 200KHz. In a very short it time proved to be a very " user-friendly " timer / integrated circuit for both simple and quite complex monostable as well as brilliant astable (or multi-vibrator) applications.  Many products owe their success to this humble little NE-555 timer. Many early security alarm systems, police sirens, ultrasonic detection equipment and various other products have benefited from this humble but so very versatile little NE-555 chip.       

The NE-555 was invented by a clever Swiss born gentleman by the name of Herr. Hans. R. Camenzind. ( Pictured ) in 1970, the NE-555 went on to become a legend in the Electronics industry, the chip possibly deriving its "nick-name"  from the three   5 K internal resistors, designated simply as R7, R8 and R9, all of which form the very unique   "five - five - five"   resistor divider combination within the chip. Herr Camenzind was born on January 1st 1934, Zrich, Switzerland in 1934.

Hans Rudolph Camenzind died August 8th 2012, Los Altos, California, USA.

Since this versatile little device became commercially more available in May 1971, a plethora of highly innovative and very unique and "ever-so-ingenious" circuits has emerged.  Many circuits have been developed and have demonstrated to the "N-th" degree in a variety of highly reputable " trade-only " journals, professional " Engineering Monthly " magazine journals as well as the vast numbers of truly excellent " Hobbyist / Professional "  publications globally,  and the likes of the extremely well presented Australian Magazine, such as Leo Simpson's SILICON CHIP, The  U.K.'s   ELEKTOR   and the  U.K.'s   Practical Electronics (PE).   Lastly and certainly not forgotten, Electronics Australia (EA) & Electronics Today International (ETI), were casualties of economics.     All of these fine publications have featured many articles over the years on the uses of this chip.   

During the past twelve or so years since May  1971 ,some   " NE-555 "   manufacturers have ceased existing in the market ,   perhaps to stiff competition,   or purely being consumed as a   " valued asset "   by much larger companies "swallowing-up" smaller manufacturers, thus perpetuating their guaranteed income from its highly successful and the lucrative sales of this   ever so popular chip, the popular NE-555 chip.  

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Click here to read this and make up your own mind

Update: 29th March 2003

Please note: Electronics Australia (E.A.) and Electronics Today International (E.T.I.) have ceased
to be published, leaving only the brilliant Australian monthly "magazine" SILICON CHIP as the only
high quality professional Electronics magazine still published in Australia for both the " Hobbyist " and
" Professional " users alike.Check out Silicon Chip Magazine right here or later on.

SILICON CHIP is available monthly from   Jaycar   or    Altronics Stores,   local newsagents or mailed directly to you by a subscription with the publisher,   in Australia and New Zealand,   phone your local store first as S. C. moves quickly off the shelves.    Local and International readers, we invite you to subscribe to   SILICON CHIP   for current updates in the Electronics and Hi-Fi/Radio industry as well as greatly researched electronics specific articles,   Serviceman's yarns, hints and tips,   New Product tests and excellent cutting edge an very innovative   " do-it-yourself "   electronic projects.

Many other companies, ( 22 to date ) like N.T.E. ( a subdivision of Philips ) have picked up where some " left off ".

See the NE-555 Manufacturers list we have compiled.

This re-structuring of Philips was followed by the formation of a new   "brand name"   in semiconductors  N X P. The following article is concentrated on this fantastic little timer IC which is, after 25 years ( 1996 ), was still very popular today ( March 1996 ) and highly used in a plethora of schematics that can be viewed on the " internet "    
Slowly a new generation of   "useful chips"   called PIC chips are taking over for many functions, these seem to be the greatest and possibly the most innovative thing to hit the market since the introduction of the now famous   "NE-555".

The PIC Chip introduced some years back has the brilliant capability of being able "programmed" just like a small CPU  and to be custom tailored via very small and byte efficient programs to execute a myriad of unique functions, from sirens, monitoring etc. to very accurate timers.  In this article (only this page) we will deal solely with the "NE - 555" applications and the easy to setup usefulness of this chip [ 1971- 1996 ]. Although these days, the CMOS version of this IC, like the Motorola MC1455, is mostly used, the regular type ( non CMOS ) is still very much available and used often today, it is still in great demand due to the simplicity in its design, efficient switching characteristics and its very low cost.

There have been many improvements and variations in the "internal" circuitry since 1971, too many to list here, however, we invite you to check out our NE-555 PDFs covering many package versions of this rather unique and special chip.

With all these "hidden" improvements within the various NE-555's manufactured, the main NE-555 package is still very much virtually pin-for-pin compatible with every other NE-555 on the market today, this also includes the NE-7555 a later marketed CMOS version of the NE-555. The aim within this simple tutorial is to show in some easy to comprehend detail, exactly how the NE-555 timer is correctly used.

The standard NE-555 can be a stand-alone compact device, yet powerful enough to perform basic timing functions or as a versatile timer or even as a simple oscillator to create tones of various pitches up to the ultrasonics of 200KHz. The NE - 555 can be easily combined with other ancillary circuitry employing gates or transistors for current switching or with other solid state devices without the mandatory requirement of an electronics engineering degree.   How good is that ?   It does not get any better ! This brilliant timer uses about 25 transistors to perform the tasks and is coupled with various diodes and resistors all on the NE-555's substrate "die" to do their bit in switching and timing and for this task, it is done with the minimum of external passive components.

Shown here, is a more simplified and accurate block diagram in Fig.3 to explain the basic internal organizations of the NE-555.

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NE-555 Manufacturers

In Table 1 ( above ), we have alphabetically listed 27 types of NE - 555 manufacturers, both past and present  ( as at December 2007 ) with their part numbers.        Some are listed under two part numbers,   check with our's or other's data sheets for   Military specification or MIL SPEC.   Some are ceramic cased.    These are reported to have some what improved electrical and thermal characteristics over their commercial generic counterparts and are " more " expensive in comparison to the generic   NE-555   sold throughout the world via electronics wholesalers and retailers such as ourselves and are typically the standard 8 PIN Dual In Line or   (D.I.L) plastic package.      We can supply MIL SPEC as requested at a higher that normal price. We believe that both the ceramic and the round T-05 or " tin can " packages are still available at the time of writing this page.

Note: A recent innovative company, Custom Silicon Solutions Inc, has produced a "hybrid" variety of the famous NE-555 with is very own six-decade programmable counter, an on-board EEPROM and the CSS-555C includes an internal 100pF timing capacitor. It is pin-for-pin compatible with the standard 555 timer and features an operating current under 5A. Its minimum supply voltage is 1.2V, making it brilliantly ideal for battery operated applications as well as a variety of other low power consumption devices. Smart and innovative, this CSS-555C !

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MIL SPEC. or Military Specification.

While on the subject of   MIL. SPEC. or   Military Specification,   it is generally not realised that Mil. Spec. chips are basically the same as any other chip, however their AQL or Acceptable Quality Level is tightened right down and the permissible errors in a sample batch of, say, 1,000 chips, 10% are tested first of all in the sample batch and if there are no errors or there are virtually zero errors, that is to say, in say the sample batch of 100 chips, 99% passed with flying colours and   1%   is a "bit suss" and pass all basic functionality tests however they do not meet the 100% AQL and therefore can be safely sold as garden variety commercial chips. 

How it works is simple, you have a run of parts, widgets, ICs, resistors or whatever mass produced product and you need to know what the error level is. What is done is, let us visualise 100,000 ICs . You need to know if they pass or fail in any way. Out of this 100,000 ICs, there is a calculated formula for the sample batch to be removed for testing. In that sample batch for testing, let us say a sample of 100 ICs are to be "Burn-In Tested".

These are fully tested with what is termed a "burn-in " test. That is to say, they are run at there very limit for several hours, days or weeks at their maximum voltage, maximum switching frequencies to evaluate if any become problems. If no errors or failures appear, then the batch is put aside and another batch sample taked from further down the "line", let us assume the batch is number 60,000 to 60,100 this batch. 100 taken out and tested. The same testing is run over hours, days or weeks and if all is fine, anothe batch taken and so on.

Here is the interesting bit.  If an error was discovered in the batch, it is noted, the batch is put aside and marked accordingly and the sample is widened to include further numbers from various stages in the run.If that testing reveals further failures, then the sample is again widened to increase the posibility of finding further failures.

Once the sample batch has exceeded a set formula it is then deemed to be a faulty batch and rejected by Quality Control. Being that production techniques are so well managed these days, high use of advanced clever photo-lithography, so the chances of it happening are so slim that one could almost take wagers on the full outcome of a batch.

There is a set down procedure for Quality Control on manufacturing best practices and is closely adhered to by manufacturers, whether it is for ICs, food or even toys. Thankfully cars are not tested in this manner. ;-)

Having said that, one can purchase a batch of, say 500 pieces of NE-555 chips and test every single chip, one chip at a time for all the correct parameters "per the data sheet". This will ensure that each and every chip is fully functional, have each chip "burned in" at its maximum recommended supply voltage, perhaps overnight or a week, on a specific "test bed" and see how many pass or fail, the passes "could" basically be classed as "Mil. Spec".  

The strange thing is, if only 100 are tested from a batch of,   say 500, this would perhaps strongly indicate a compliance to the manufacturer's data sheet specifications or better.  To do this, requires a great deal of precision test equipment, special high stability power supplies and a host of test equipment costing thousands of dollars !

Also, having noted that, it would be safe to say that certain chips in that control batch of a mere 100 chips could actually perform a small percentage better than others in the batch, it would be unreasonable not to expect this result from a quantity of only 100 pcs of mass manufactured NE-555 chips or in fact any other type of semiconductor manufactured these days. It does not get any better than this !

This however dispels the   myth   and story that manufacturers make special chips,  manufactured with extra bits or thicker substrate, thicker attaching wires, increased substrate pads areas and so on, to special specifications, calling them MIL.SPEC.    It simply is not so.

This is so different in contrast to Military specification equipment. Take for instance ruggedised laptops made for the Military. These are by their very nature built to a strict guideline and stringent specifications whereas they can be dropped from a certain height, kicked, be blown up in a Army tank (only kidding here) and still boot up and survive.

Why does this occur ?   They are designed from their inception to be the best of breed.

Panasonic has earned a great reputation for making very rugged laptops for use by the Military. They have earned their place in manufacturing durability, reliability and performance, as have several others.

We invite any LINEAR, LOGIC or ANALOG chip manufacturer to write to us and prove us 100% wrong.

Our email is:

To date, not one chip manufacturer has written to us to explain
that there are in fact specially manufactured chips as MIL. Spec.

Figure1 555 pin-out

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The NE-555, in figure 1 (above) is supplied in a plastic package. It is believed that the round metal-can called the ' T-05 ' package or the "tin-can" is no longer available in favour of the more familiar and cheaper to produce 8-pin DIP "Dual IN-Line plastic" package. About 20 or so years ago the "T-05" metal-can type was very much the standard with the early SE-555 and NE-555 types .

The NE-556 timer is a dual version of the NE-555 and comes in a standard 14-pin DIP plastic package, with two NE - 555 timers within.

The NE-558 was a quad version of the NE-555 with four distinct NE-555's within the one package, incidentally in a 14 pin DIP case, however it was scheduled to be discontinued due to its lack of popularity and also more importantly, its own inherent internal "noise" problems.

Fig.3 NE-555 Block Diagram

Within the NE-555 timer, in figure 3 (above) there are the equivalent of over 26 semiconductors and about 15 resistors, depending on the actual manufacturer. The representative equivalent circuit depicted in Fig.4 B here in block diagram, shows the provision of the functions of "control", "triggering", "level sensing" or "comparison", "discharge" and most importantly, the "power output". Note the three 5K resistors. Note: The use of C2, typically 10 Nanofarads (nF) assists in "good house-keeping" in keeping "internal noise" down. It accesses directly the inverting input of the upper comparator which is incidentally connected (inside the chip) between the first and second of the 5K resistors which will be discussed further on in this tutorial , down the page under the heading   Pin 5 ( Control Voltage ).

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Some of the more attractive features of the recent NE-555 timers are: Supply voltage between 4.5 volts and 18 volt, supply current of between 3 to 6 mA and a Rise / Fall time of 100 nSec.

The NE-555 performs best with a stable supply voltage with good low ESR filter capacitors to keep the "lines" clean.

It can also withstand quite a considerable amount of "reasonable" abuse, though it does not handle reverse polarity power.

Note: in Figure 3 ( above ) the common threshold current is in fact determined by the maximum value of    Ra + Rb. For typical maximum 15 volt operation the maximum total resistance for R ( Ra +Rb ) is  20 Meg Ohm, please bare this in mind.

The supply current, when the output is 'high', is typically around 1mA (milli-Amp) or less. According to the specs, the initial monostable timing accuracy is typically within 1% of its "calculated" value, and exhibits negligible ( 0.1%/V ) drift with regards to supply voltage.

Thus it can be realised that long-term supply variations can basically be ignored and the temperature variation is only 50 ppm / C ( 0.005% / C ).

R - C Networks All IC timers rely upon an external capacitor to determine the off-on or on-to off time intervals of the output pulses.

You may recall from your own personal experiences in a study of basic electronics,   it takes a finite period of time for a capacitor (C) to charge or to discharge expotentially through a resistor ( R ).  Those times are clearly defined and can be calculated given the values of resistance and capacitance.  

The basic RC charging circuit is shown in fig. 4.( below )   So, assuming for a moment that the capacitor  ( C ) is initially discharged, when the switch is closed,the capacitor begins to charge through the resistor via Ra and RB.     The voltage across the capacitor rises from zero up to the value of the applied DC voltage.    

The charge curve for the circuit is shown in fig. 6 (below).   The time that it takes for the capacitor to charge to approx. 63% of the applied voltage is known as the time constant (t).   That time can be calculated with the simple expression:

Looking at the voltage charge versus time curve in figure 6. you can see that it takes approximately "5 complete time constants" for the capacitor to charge to almost the applied voltage. Theoretically, it would take about 5 seconds for the voltage on the capacitor to rise to approximately the full 6.0 volts.

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Figure 4 & 6 - NE-555 Timing

t = R X C

Let's assume that a resistor in this circuit has a value of 100K ohm and that the capacitor's value is 10 µ (Micro-Farad).

The time constant in this case is:

t = 100,000 x 0.00001 = 1 second

Let's further assume that the applied voltage is exactly 6.00 volts, just for a round figure.

That is to state that it will take one time constant for the voltage across the capacitor to reach the approx. of 63 % of the applied voltage of 6.00 volts.

Therefore, theoretically, the capacitor charges to "approximately" 3.78 volts in approximately one second.

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Fig. 41 - Pulse change

In Figure 4 A (above), a change in the input pulse frequency allows for the completion of the timing cycle. The accepted rule is that the monostable 'ON' time is set to approximately 1 / 3 longer than the expected time between the actual "triggering pulses". Create your own " test circuit " and observe it on your C.R.O. or D.S.O. This circuit is more often referred to simply as a " Missing Pulse Detector " circuit.

Fig. 4-2 -Equivalent Circuit

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Pin 1 Ground    Pin 2 Trigger    Pin 3 Output    Pin 4 Reset

NE555 Data

Pin 5 control voltage    Pin 6 Threshold    Pin 7 discharge    Pin 8 +Vcc

Definition of Pin Functions:   Refer to the internal 555 schematic of Fig. 3 (above).

Pin 1 ( Ground ) :

NE-555 Pin 1 gif
The ground ( Earth, Deck or Common ) pin is the negative (-ve) voltage supply of the device, which is connected to circuit common (ground) when operated from positive (+ 4.5V - + 15V DC) supply voltages. This pin is ALWAYS grounded.

NE-555 all tied up png

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Pin 2 ( Trigger ):

NE-555 Pin 2 gif

Pin 2 is the access "input" to the lower NE-555's comparator and is used to set the latch, which in turn causes the output to go high. This is the initialising of the timing sequence in monostable operation and the triggering process is accomplished by taking the pin from "above" to "below" a voltage level of 1/3 V+ or, in general, 1/2 of the apparent voltage appearing at pin 5. This action of the triggering the input is "reasonably" level sensitive, thus allowing notably slower rates of change in the wave forms, as well as "pulses", it can also be used as "triggering" sources.

Note that the trigger pulse must actually be of shorter duration than the time interval determined by the external R and C. When pin 2 is held low longer than that, the resultant output will remain high until the trigger input is driven high once again.

One precaution that should be observed with the trigger input signal is that it must not remain lower than 1/3 +VCC for a period of time longer than the timing cycle. If this is allowed to occur, the timer will always re-trigger itself upon termination of the first output pulse. Thus, when the timer is driven in the monostable mode with input "pulses" longer than the desired output pulse width, the input trigger Pin 2 should effectively be shortened by differentiation. This fact can be a useful feature.

The minimum-allowable pulse width for actual triggering is virtually dependent upon pulse level, but in reality if the pulse is greater than the 1 micro-Second (uS), general triggering will be quite reliable. Always be mindful and take precautions with the "storage" time in the lower comparator. Always bare this in mind in your designs, especially in "tight" timing circuits.

This area of the NE-555 circuit can exhibit normal "turn-off" delays of several (uS) microseconds after triggering, ie: the latch can still "hold" a trigger input for this period of time after the trigger pulse. Spooky eh? Not really, in reality this means that the minimum "monostable" output pulse width should be in the order of 10uS (micro-seconds) to prevent possibility of double triggering due to this unusual effect.

The input voltage's range that can be quite safely applied to the trigger pin 2 is anywhere between +Vcc and ground, or basically +ve supply and zero. A "dc current", termed the Trigger current, must also flow from this terminal into the external circuit. This flow of current is typically around 500 nano-Amps (nA) and will define the upper limit of resistance allowable from pin 2 to ground. This of course will vary from one manufacturer to another.

For an astable (multivibrator) configuration operating at +VCC = 5 volts, this resistance is about 3 Mega-ohm, however it can be greater for higher +VCC levels but not to exceed 10 Meg Ohms.

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Pin 3 ( Output ):NE555 Data
NE555 Pin 3 gif

The output Pin 3 of the NE-555 comes from a high-current pseudo "totem" pole arrangement made up of internal transistors Q20 - Q24. Transistors Q21 and Q22 in a "Darlington" configuration, provide the drive for source-type loads, whereas Q22 is performing the switching here. The Darlington configuration provides a high-state output voltage of around 1.7 volts less than the +VCC supply level used.

The Q24 transistor provides current-sinking capability for low-state (low Logic) loads referred to +Vcc ( as found in typical TTL inputs). Q24 also maintains a low saturation voltage, which allows it to nicely interface directly, while facilitating a good noise margin, when delivering current sinking logic levels. Q20 is the main culprit is doing the "official" switching is Q17, outputs depend on what is at Q17's base.

It is true to state that output saturation levels vary markedly with relation to supply voltage, it can however be said that the same rule applies to both high states and for low states. At a +VCC of 5.00 volts, for a example, the low "logic" state Vce ( sat ) can be measured at around 0.25 volts at a mere 5.00 mA. While operating at 15.00 volts, however, it can easily sink 200 mA if an output-low voltage level of around 2.00 volts is permissible, bearing in mind that the general total power dissipation should be always noted in all such instances. NE-555 chips can indeed get very hot when "over-driven" and this factor alone can affect the internal stability by continued operation at much higher temperatures.

An important or even perhaps a crucial suggestion would be to add an external "drive" transistor that can handle an increased load in line with current considerations (see Fig. 5B) the pin 3's "load" with a transistor and its base drive resistor with the desired current switching in mind from pin 3.This transistor can be anything from a humble small 800 mA current switching 2N2222 to a BD681 Darlington switching around 4 amps. Both will work.

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Pin 3 ( Output ) Cont'd:
What is termed a "high-state" level or logic high is to the order of about 3.3 volts at +Vcc = 5.00 volts, about 13.30 volts at +Vcc = 15.00 volts.

Note that both "Rise" and "Fall" times of the output waveform are typically quite fast, with average switching times being to the order of around 100nS (nano-Seconds).

Nothing in general electronics is 100% absolute, hence the use of terms "around" and "about", due to component tolerances.

In doing your timing/switching experiments, always observe the fast switching characteristics on a C.R.O.   (Cathode Ray Oscilloscope) or a L.C.D. D.S.O. (Digital Storage Oscilloscope).

When using a RX external transistor, Figure 5 B make sure the base is saturated just enough with input voltage / current but not overdone. That is to say, not being "over-driven" with regards to driving the base of the transistor too hard, thus possibly frying the transistor.

This could be any value between 820 Ohms up to 3K3 or beyond, depending also on the voltage / current consumed by the switched device, for example, a 300 Ohm relay. Do your maths and calculate the desired switching voltage / current.

The state of the logic state of the latch will always be the reverse of the output pin 3, and this fact may be observed by examining Figure 3.   Block-layout

Since the latch itself is not directly accessible, this relationship may be best explained in terms of latch-input trigger conditions. To trigger the output to a high condition, the trigger input is momentarily taken from a higher to a lower level. [see "Pin 2 - Trigger"].

This causes the latch to be set and the output to go high logic. Actuation of the "lower" comparator is the only manner by which the Pin 3 output can be switched to a high logic state.

The Pin 3 output can revert to a low state of logic by allowing or forcing the "threshold" Pin 6 to go from a low state of logic level to a higher state logic level (see "Pin 6 - Threshold"), which resets the 555's latch. The output can also be made to go low by taking the reset to a low state near ground (see "Pin 4 - Reset"). The output voltage available at this pin is approximately equal to the Vcc applied to pin 8 minus 1.7V.

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Pin 4 ( Reset ):NE555 Data
NE555 Pin 4 gif

Pin 4 is used to "reset" the NE-555/s internal latch and restore the output to a low logic level.

The actual "reset" voltage threshold level is about 0.7 volt, and resetting requires a sink current of around 0.1mA to perform the reset of the NE-555 chip.

These levels operate fairly independently of the operating +Vcc level, resulting in the reset input being TTL compliant with any supply voltage between 4.5 Volts and 15 Volts D.C.

Pin 4 the reset input is an over-riding function, that is to say, it will actually force the output to a low logic state with total disregard of the state of either of the other "inputs".

It can be employed to terminate an output "pulse" earlier than expected or to gate oscillations from an "ON" state to an "OFF" state etcetera.

The delay timing from resetting to output is typically on the order of about 0.5 S, and the minimum reset pulse width is around 0.5 S. These timing figures are "generalised" and will vary from one NE-555 manufacturer to another, based on tolerances and "die" lithography, processes and assembly.

Pin 4, the reset pin is primarily used to specifically reset the flip-flop that controls the logic state of output from pin 3. The "reset" pin is activated when a level as low as 0 (zero) and up to 0.4 volts voltage is presented to this pin.

Pin 4 once activated, will in turn force Pin 3 to drop to a low logic level irrespective of what state any of the other inputs to the internal Flip-Flop are. Basically it over-rides all. In utilising the NE-555, we suggest tying this pin to +VCC in most situations where the reset pin is not being directly employed as such.

This will avoid a "false" reset situation whereas the NE-555 in some circumstances could possibly reset without notice.

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Pin 5 ( Control Voltage ):NE555 Data

NE555 Pin 5 gif

As mentioned earlier, the NE-555 has three 5K ohm resistors (R7, R8 and R9) in series forming an equal voltage divider thus as 1/3rd, 2/3rd's within. Pin 5 provides for direct access to the 2/3 +Vcc of this unique voltage divider reference point, the referenced level for the NE-555's upper comparator. It also facilitates indirect access to the lower NE-555's comparator, as there is a 2 : 1 ratio divider via R8 and R9 from this point to the lower-comparator reference input at transistor Q13.

It is in fact optional to utilise this pin 5. It can be called a "user pin" and it does allow some unique flexibility by permitting alteration to the timing period, re-configuring the R7 value to less than 5K ohms thus customising the "resetting" of the comparator, etcetera. When the NE-555 timer is used in a "voltage controlled" mode, its operational ranges will vary from about 1.00 volt less than +VCC and down to within 2 volts of ground, although this is not guaranteed in print on the NE-555 specifications sheet.

Voltages lower than 15 Volts (maximum supply voltage) can be safely applied outside these limits, however they should realistically be confined to be within the limits of +VCC and ground (0V) for higher reliability.

By applying a voltage to Pin 5, it is in fact possible to vary the actual timing of the device totally independent of the RC network. The control voltage may be varied from around 45% to about 90% of the +Vcc in the monostable mode, making it quite possible to control the width of the output pulse quite independently of RC. When it is used in the astable mode or ( multivibrator) mode, the control voltage at Pin 5 can be varied from around 1.7V to the full 15V +Vcc and not over.

Indeed, by varying this voltage at Pin5 in the astable mode, it will produce a frequency modulated (FM) output.

IF the control voltage Pin 5 is not used, it is recommended in the specifications that it be bypassed, to ground (0V), with a capacitor of about 10nF (nano-Farads) for good immunity to noise on the upper comparator's input (non-inverting). It is not quite obvious to perform this as in many NE-555 circuits we have seen since have absolutely no by-pass capacitor off Pin 5 to ground. After reading the NE-555 specifications sheet, one can realise the good value in adding this capacitor.

Don't skip doing it. The small 10nF ceramic cap may also eliminate false triggering and let's face it, they are cheap.

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Pin 6 ( Threshold ):NE555 Data

NE555 Pin 6 gif

Pin 6 is one input to the upper comparator ( inverting ) the other being Pin 5 which is used to reset the latch, which results in the output to going low logic. A reset of the NE-555 can be accomplished via Pin 6 by taking Pin 6 from below 2/3rds +VCC to above a voltage level of 2/3 +VCC which incidentally is about the normal voltage on pin 5.

The action of the threshold Pin 6 is fairly "level sensitive", allowing for slow rate of change type waveforms.

Build your very own NE-555 tester and observe these various readings on your oscilloscope.

Note the noise on the power source input +VCC if there are no filtering capacitors to clean up the inherent noise from within the NE-555 chip.

Add more "filter" capacitors and see the difference for yourself. Remember Pin 5 with its own 10nF ceramic capacitor.

The wave forms are fascinating to watch and learn from and apply to other useful project directions.

At Pin 6 the voltage range that can safely be introduced to the threshold Pin 6 is between +VCC and ground or earth / 0V.

A "DC current" referred to as the Threshold Current must also flow into Pin 6 from the external circuitry.

This "DC current" is typically to the order of around 0.1µA,( Micro-Amp) and will actually define the "upper limit" of the "total" resistance allowable from Pin 6 to +VCC.

For either timing configuration operating at +VCC = 5.00 volts, this resistance is very close to 16 Meg-ohms. Use your DMM ( Digital Multi-Meter ) . Always check ( if you have a known high resistance resistor ) to get a reference reading.

Doing the maths, For 15.0 volt operation, the maximum value of resistance is around 20 Meg Ohms.

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Pin 7 ( Discharge ):NE555 Data

NE555 Pin 7 gif

Pin 7 is connected to the Open Collector of Q14, an NPN transistor, the emitter is connected to ground, so that when the Q14 transistor is turned "ON", Pin 7 is directly "shorted" to ground potential. Typically the timing capacitor C 1 is connected between Pin 7 and ground 0V and is discharged only when the transistor turns "on". The conduction state of the Q14 NPN transistor is basically identical in "timing" to that of the "output" stage.

It is "on" [ ie: low resistance to ground ] when the output is low and "off" [ high resistance to ground ] when the output is high. In both the monostable and astable ( multivibrator ) time modes, the Q14 NPN transistor switch is used to clamp and hold the appropriate "nodes" of the timing network to ground 0V. The Q14 base saturation voltage is typically below 100mVs (milli-Volts) for designated currents of around 5 mA or less and the off-state leakage current is about 20nA (nano-Amps) measurable (only just). Note this is not as far as we know, written in the NE-555 spec sheet.

Note: The maximum collector current of Q14 NPN transistor is internally limited by the design, thereby removing any possible or potential restrictions on the capacitor C 1's size due to peak "pulse" current discharge. We suggest not using capacitors as high as, for example, 4700 uF as the collapse current may do some internal damage to the NE-555's Pin 6 open collector Q14 NPN transistor. Be very much aware of this factor.

In certain circuit applications, this open collector Q14 NPN transistor output can be used as a pseudo- auxiliary output terminal, with its own small current sinking capability similar (but not as high) to the output (pin 3).

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Pin 8 ( Vcc +ve ):NE555 Data

NE555 Pin 8 gif

The +VCC Pin 8 is the positive supply voltage pin of the NE-555 timer IC. The supply voltage operating range for the NE-555 is + 4.5 volts (minimum) to +15 volts (maximum), and is specified for operation range of between +5 volts and +15 volts. The NE-555 timer device will operate basically the same over this wide range without any noticeable change in timing period. The most significant notable operational difference is the output Pin 3 drive capability, which increases for both current and voltage range as the supply voltage is increased.

Sensitivity of the time interval to supply voltage change is typically very low, usually around 0.1% per volt or less.

Note: We discussed Military specification chips previously and there are claims that special and "MIL-SPEC" military devices are available that operate at voltages as high as 18 volts. As mentioned, a control batch of , say 100 chips of NE-555 will exhibit various "operating characteristics" though, it is rumoured that some NE-555's do run as high as 18 Volts D.C. We need to test these before we can safely state that this is in fact correct and the details above will be alter to reflect these "testing" results. (1996)

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Safety First is our priority- Be aware of 240V mains

NE-555 Pocket tester - A Simple go / No-Go tester
Figure 5 - NE-555 timer Tester

Figure 5A - NE-555 timer Tester layout

Build yourself a simple NE-555 test circuit of Figure 5 (above) to get you going and test all your NE-555 timer IC's. You can instantly check to see if they are functioning. Another use is as a NE-555 "trouble shooter" circuits. This tester will tell you if it's a goer. Make sure the NE-555 goes in the correct way as per the drawing. Otherwise, smoke may will result !  Remember this rule, never ever oscillate an old NE-555 I.C. in excess of 200 KHz, smoke may occur ! The newer Y2K onwards types will sing at 300KHz.The circuit is kept as simple as need be, there are no filtering caps, no inductors etc. You will of course, require a good quality 8 pin IC socket. Machine sockets are the most ideal, followed by dual wipe.

In Figure 5A we have provided you with a Vero-Board layout complete with all cuts made to form the circuit.

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Safety First is our priority- Be aware of 240V mains

Layout is Copyright 1996 Unitech Electronics Pty. Ltd. ALL RIGHTS RESERVED.
First updated: Copyright January 28th 1996 - - 2015 and onwards.

The most recent updates to the NE-555 pages only:
( 00 ) Started the NE-555 pages in one very long page: May 16th 1997. 
( 01 ) Added PDF access references: September 21st 2009.
( 02 ) Added 1 Hz Oscillator improved clearer calcs text: March 23rd 2010.
( 03 ) Added 1 Hz Oscillator Pic Fig 14 and text: March 23rd 2010.
( 04 ) Added NE-555 Calc and pic of 1 Hz Oscillator Pic: March 23rd 2010.
( 05 ) Fixed problems in viewing with Internet Explorer it had with the simple HTML. No problems with Firefox : March 25th 2010.
( 06 ) Cleaned up html & text for bug in Internet Explorer 7 "weird feature". No problems using Firefox: March 29th 2010.
( 07 ) Added a sub menu denoted as FREE NE555 CIRCUITs 18 added so far....12 more to come : April 2nd 2010.
( 08 ) Refining slight imperfections in gifs and correcting spelling mistakes: April 4th 2010.
( 09 ) Added 38 new "click-on" gadgets to simplify navigation on this page : April 5th 2010.
( 10 ) Added NE-556, NE-558 and ICM-7555 PDF datasheets and their "click-on" gadgets: April 7th 2010.
( 11 ) Added 7 more "click-on" gadgets to assist in better navigation of this page: April 8th 2010.
( 12 ) Fixed HTML conflicts discovered in Internet Explorer but work fine in FireFox: April 8th 2010.
( 13 ) Note: Conflicts discovered with "mouse-over", the moving chips fail to halt under Internet Explorer: April 8th 2010.
( 14 ) Added more Gadgets:- TOP, NE-555 Data PDF and Back to Free circuits to navigate the page better: April 11th 2010.
( 15 ) Added even more Gadgets:- NEXT UP, NEXT DOWN, and tidied up some gifs to navigate around the page better: April 20th 2010.
( 16 ) Added more PDF icons to assist in navigating the page better. Added Vero-board for 555 tester: April 22nd 2010.
( 17 ) Added CSS-555C PDF icon and its relevant text information and Shrunk Table 1: April 25th 2010.
( 18 ) Added Fig 5A NE555 Tester Coloured components overlay and revised VeroBoard colourings: May 16th 2010.
( 19 ) Upgraded the page, new colours..improved layout, easier on the eyes, this will take time to line everything up.: July 17th 2011.
( 20 ) After going over the texts, three spelling errors were corrected. : July 21st 2011.
( 21 ) Upgrading the texts, lining them so as to print out better. 37 pages printed out of this single web page. : August 15th 2011.
( 22 ) Bug Found! The moving NE-555 chips fail to move under Google Chrome ! also this splattered text: August 16th 2011.
( 23 ) Stupid Windows Internet Explorer 7 & 8 still "sees" the HTML coding as running scripts or worse Active X which it is not
( 24 ) NE-555 page split into three separate pages, thus making it quicker to load per page November 26th 2011.
( 25 ) Shrunk the OM802 page to suite Tablet devices. August 12th 2012.
( 26 ) removed the moving NE555 chip that distracted on most NE-555 pages August 12th 2012.
( 27 ) Revised and shrunk the " NE-555-4-WAY.htm " page in line with tablet capabilities. August 13th 2012.
( 28 ) Converted the NE555TIMERN.wmv  to  NE555TIMERN.avi thus reducing the file size. October 21st 2015.
( 29 ) Cleaned up this page and arranged the text to read and print out better. October 27th 2015. 

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